Download SimpleSolver, Simple Solver Boolean and Logic Simplifier, Download Simple Solver Boolean and Logic Simplifier, SimpleSolver is a free Windows application for design and minimization of Boolean equations and digital logic systems.Â Users are worldwide, as depicted in the global map above.

**The software includes six integrated tools which provide a wide range of digital design capability:**

- Â»Â Â Boolean minimization
- Â»Â Â Logic schematic drawing â€“ new
- Â»Â Â Automatic logic design
- Â»Â Â Logic circuit simulation
- Â»Â Â Permutation & Random number generation

**SimpleSolver tools are designed to be:**

- Â»Â Â Very easy to use
- Â»Â Â Very fast with high capacity
- Â»Â Â Extremely efficient for design – many unique capabilities
- Â»Â Â Educational for both students and experienced engineers
- These tools are built on years of computer-engineering design experience.Â They are intended for both educational and industrial usage.

### Boolean Logic Minimizer

The Boolean logic (Boolean algebra) software can be used to rapidly design truth tables and to minimize Boolean equations.Â Equations and truth tables can have from 1 to 20 variables.

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- Output Options
- Comment Lines â€“ Input comments
- Input Eqn / TT – Input equation or truth table
- Truth Table full – Complete truth table
- Minimize – Minimized equation
- Invert & Minimize – Minimized complemented equation
- Align Minterms – Or-terms aligned vertically
- PLA Minimize – Minimized equation in PLA format
- Sort Terms – Sort variable names and minterms
- Logic Design – Truth table formatted for Logic Design Auto
- Operator Format – VHDL VB, PALASM, ABEL, C C++ Verilog

### Logic Design – Draw & Simulate

Logic Design Draw (LDD) is a graphical WYSIWYG tool that enables a user to quickly create a logic schematic diagram and simulate it.

Circuits can be very simple, such as and-or logic, or can consist of hundreds of parts.Â Both basic parts (logic gates, flip-flops) and MSI (Medium Scale Integration)Â building blocks are provided.

LDD has two primary windows – the Design window and the Simulation window:

In the “Schematic” mode, the Design window can be used to build a schematic diagram of the circuit, while in the “Macro Block” mode the schematic diagram can be converted to a single block which can be saved as a new part.

**Logic Circuit Library**

- Logic gates – buffer, inverter, and, or, nand, nor, xor, xnor
- Flip-flop types – D,Â J-K Â Â Â Â Â Oscillator – (4) frequencies
- Memory – ROM read-only memory, RAM read-write memory
- 54LS MSI functions – decoder, encoder, multiplexer, binary counter, shift register, arithmetic logic unit.
- Additional MSI functions can be built using the LDD Macro Block mode.

### Logic Design – Auto

The Logic Design Auto tool automatically designs, minimizes and simulates small digital logic circuits.Â All types of digital logic are supported:Â Combinational – Sequential – Synchronous – Asynchronous.

### Logic Simulator

The free Logic Simulator simulates digital logic circuits and state machines that are defined by a text file. Â Both basic parts, such as logic gates and flip-flops,Â and MSI (Medium Scale Integration)Â functions are supported.

### Permutation Generator

The free Permutation software calculates permutation quantities for a Base number from 1 to 999 and a Number of Digits from 1 to 99. If enabled, permutation number/name groups are also be generated and displayed.Â Up to 250 MB of data can be stored.

### Random Number Generator

The free Random Number software generates from 1 to 99,999 random numbers in a specified range of -99,999 to 99,999. The randomizer software is initialized by using the system timer as the new seed value.

**Minimizer Algorithms**

Boolean logic (or Boolean algebra) minimization generally follows a Karnaugh map approach, also known as a Veitch diagram, K-map, or KV-map.Â The Boolean Minimizer software uses both Quine-McCluskey and Espresso(Â© UC Berkeley)Â algorithms to implement Karnaugh mapping and to optimize minimization.

In contrast, the Logic Minimizer software performs automated logic design by searching for circuits that match the transfer function specified by the input and output signal waveforms.Â Because the search begins with the smallest number of gates or flip-flops,Â the first circuit solution found will generally be the simplest possible solution.

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